Freescale Semiconductor /MKW20Z4 /XCVR /TSM_TIMING05

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TSM_TIMING05

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PLL_REF_CLK_EN_TX_HI 0PLL_REF_CLK_EN_TX_LO 0PLL_REF_CLK_EN_RX_HI 0PLL_REF_CLK_EN_RX_LO

Description

TSM_TIMING05

Fields

PLL_REF_CLK_EN_TX_HI

Assertion time setting for PLL_REF_CLK_EN TX sequence.

PLL_REF_CLK_EN_TX_LO

Deassertion time setting for PLL_REF_CLK_EN signal or group TX sequence.

PLL_REF_CLK_EN_RX_HI

Assertion time setting for PLL_REF_CLK_EN signal or group RX sequence.

PLL_REF_CLK_EN_RX_LO

Deassertion time setting for PLL_REF_CLK_EN signal or group RX sequence.

Links

() ()